Deep junction devices are used in particular for manufacturing vertical power devices such as IGBT (Insulated Gate Bipolar Transistor) or power metal-oxide-semiconductor field-effect transistor (MOS also MOSFET, MOS-FET, or MOS FET).
Numerous documents describe devices and methods for forming deep electronic junction devices. IC fabrication is achieved by completing first the front-side processing steps and then pursuing with the backside processing steps. The front-side processing is the first portion of IC fabrication where a first part of the deep junction devices is patterned on the front side of a semiconductor wafer, and the back-side processing is the second portion of IC fabrication where the opposite part of the deep junction device is formed on the back side of the wafer. Backside processing generally begins when the front side structure is finished with metallization step.
The backside processing steps must thus be performed at a temperature lower than about 450° C. in order to preserve the electrical junction and the IC metallized structures formed on the front side of the substrate. Moreover, the backside processing is preferably achieved at a low thermal budget to reduce processing costs.
Within the present disclosure, a thermal budget of a processing step is defined as the product of the temperature by the duration of the processing step at that temperature. For instance, the thermal budget for a processing step of several minutes in an oven at a temperature of more than 1000° C. is extremely high, and incompatible with backside processing.
Vertical power devices require in particular formation of a deep doped buffer layer on the backside of an integrated circuit. Within the present disclosure, a deep layer means a layer buried at a distance in a range comprised between 500 nanometers to about 5 micrometers from the back surface of a substrate.
A known technique for forming a deep doped layer relies on the use of a standard implanter followed by thermal diffusion and activation. Standard implanters are based on accelerator systems and can be classified in the following two categories. Medium current accelerator systems generate ion beam currents between 10 pA and 2 mA, with an energy range comprised between 3 keV and several hundreds keV. High current accelerator systems generate ion beam currents up to about 30 mA, for energies up to 0.2 keV-180 keV. The implantation depth depends on the mass of the implanted species. Thermal diffusion consists in placing the substrate in an oven at a temperature superior to 700° C. for minutes or hours, which implies a high thermal budget. Thermal diffusion enables activating the dopants implanted deeply in the bulk of the substrate. However, this technique cannot be applied for forming a deep doped buffer layer on the backside of an IC, because thermal diffusion exposes the frontside of the sample to a high temperature and because its long duration (minutes or hours) turns into high thermal budget.
Today the standard technique for forming a deep doped buffer layer on the backside of an IC substrate is performed in two separate steps: a first step using a high energy implanter for implanting dopant elements into the substrate, in general a monocrystalline silicon wafer, and a second step, using laser thermal annealing (LTA) so as to activate the implanted dopants. The process of high energy implantation followed by LTA is generally achieved during backside processing steps of an integrated circuits (ICs) manufacturing line, after the last step of front-side processing. Within the present disclosure, high energy implantation means implantation of dopant ions, using an ion implanter or ion gun, at energy comprised in a range from 200 keV to several MeV. The implantation depth depends on the mass of the implanted specie. High energy implantation is necessary for implanting dopant elements directly into a buried layer in the bulk.
However, high energy implantation is expensive and strongly dependent on the dopant element. Moreover, laser thermal annealing, which is generally performed at low thermal budget, is limited to the activation of some dopant elements with a limited and specie-dependent diffusion.
Other processes rely on a double implantation scheme: a high energy implantation of a first dopant element at a distance of 1 to 2 micrometers from the surface followed by a shallow implantation of a second dopant element at a distance of about 500 nanometers from the surface, so as to form a p-n vertical electronic junction.
Patent document DE 10 2006 053182 A1 relates to a method for implanting aluminium or gallium dopants in silicon by steps of less than 500 nm depth, followed by a first laser annealing step, deposition of a capping layer, another laser annealing step and a drive-in step at a temperature higher than 750° C. Publication Ong et al. relates to “A low-cost method of forming epitaxy SiGe on Si substrate by laser annealing” APL, vol. 94 no. 8, 2009, p 82104-82104.
There is a need for a simpler backside process for forming deep electronic junction devices and/or vertical power devices while maintaining the frontside at relatively low temperature (less than about 450° C.). In particular, there is a need for forming a deep doped buffer layer on the backside of an integrated circuit at a low thermal budget.